There is a phenomenon of an undesirable flow of a drain current in a field effect transistor even when a gate voltage is set to be equal to or lower than a threshold voltage. For example, due to distortion or a crystal defect in a boundary portion between an active region and a separation region of a field effect transistor, a drain current starts to flow along the boundary portion even at a gate voltage equal to or lower than a threshold voltage. Thus, there is an undesired variation in a current between field effect transistors constituting a differential pair, a load and the like in which a current balance is required. For example, JP-A-2001-144189 discloses that when a field effect transistor is formed in an element region partitioned by a trench element separation region, impurity concentration is adjusted so that a threshold voltage between both ends in the vicinity of a boundary with the trench element separation region is made to be higher than that in the central portion of its channel region.